IP Cores: How to Get There from Here

By _Cadence - The Fuller View Blog

October 14, 2013

Every time I look at the ITRS roadmap I get a little queasy. In five years, the average design is supposed to have twice the number of logic gates alone (north of 300 million). At the same time, we're supposed to double design productivity (and, presumably churn out more complex ICs because the world will continue to demand them).

Seems Herculean doesn't it?

And yet, it will happen. Why?

Consider Cisco's "mega ASIC" that EE Times' Rick Merritt reported on recently. The nPower X1 is a 4 billion-transistor chip that supports 400Gbit/s aggregate throughput.

Merritt writes: "Unlike 400G chip sets in core routers from Alcatel-Lucent and others, Cisco crammed all the packet processing and traffic management jobs—including packet buffering, queuing and scheduling—into a single whopping 598mm2 die made in a 40nm process."

Cisco believes the silicon integration gives it an edge in packing Terabit/s throughput into a single linecard using an undisclosed number of nPower ASICs. The top-end NCS 6000 systems using the chip and shipping today claim 5Tbits/s throughput per slot and 1.2Petabit/s at the system level.

So that roadmap isn't as crazy as it sounds. Consider that this is an ASIC that leverages a lot of IP; it uses, for example, 336 dual-threaded Tensilica cores in part to achieve that blazing speed.

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