AMBA moves forward with major revisions to AXI and CHI specifications
October 17, 2019
We are pleased to announce two major revisions of the AMBA specifications: Issue G of the AMBA AXI and ACE Protocol Specification and Issue D of the AMBA CHI (Coherent Hub Interface) Architecture Specification. These releases are part of the existing fifth generation of AMBA (AMBA 5) and extend the successful and widely adopted AXI and CHI interfaces. They introduce the support for key Arm Architecture features and a series of performance and transaction improvements that are aligned with the requirements for the next generation of system on chips (SoCs).
This blog post gives an overview of some of the functionality introduced in the new releases of the AXI and CHI specifications.
To read the full article, click here
Related Semiconductor IP
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
Related Blogs
- Why do I need an AMBA 5 CHI Memory Controller?
- Debug of AMBA AXI Outstanding Transactions
- AMBA AXI Exclusive Access De-mystified
- Introducing new AMBA 5 CHI protocol enhancements
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview