AMBA moves forward with major revisions to AXI and CHI specifications
We are pleased to announce two major revisions of the AMBA specifications: Issue G of the AMBA AXI and ACE Protocol Specification and Issue D of the AMBA CHI (Coherent Hub Interface) Architecture Specification. These releases are part of the existing fifth generation of AMBA (AMBA 5) and extend the successful and widely adopted AXI and CHI interfaces. They introduce the support for key Arm Architecture features and a series of performance and transaction improvements that are aligned with the requirements for the next generation of system on chips (SoCs).
This blog post gives an overview of some of the functionality introduced in the new releases of the AXI and CHI specifications.
Related Semiconductor IP
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
Related Blogs
- Why do I need an AMBA 5 CHI Memory Controller?
- Debug of AMBA AXI Outstanding Transactions
- AMBA AXI Exclusive Access De-mystified
- Introducing new AMBA 5 CHI protocol enhancements
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?