LPDDR5 Controller IP

Compare 24 LPDDR5 Controller IP from 6 vendors (1 - 10)

LPDDR5T / LPDDR5X / LPDDR5 Controller
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
LPDDR5X DDR Memory Controller
- JEDEC LPDDR5X/LPDDR5 devices compatible
- Data rates up to 8533Mbps
- Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
- Compliant with JEDEC standard for LPDDR5/4/3, DDR4/3
- DRAM rank of up to 4
- Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
- Support for dynamic DRAM frequency scaling
LPDDR5X/5/4X/4 Memory Controller IP
- Intensive DRAM Utilization
- Ultra Low Power Consumption
- Extremely Low Latency
- Safety & Security
DDR Controller
- Sideband and in-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
- Memory controller interface complies with DFI standards up to version 5.0
- Priority per command on Arm^® AMBA^® 4 AXI, AMBA 3 AXI
- Single and multi-port host interface options
- QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
- Silicon proven and shipping in volume
DDR/LPDDR Controller
- Sideband and in-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
- Memory controller interface complies with DFI standards up to version 5.0
- Priority per command on Arm^® AMBA^® 4 AXI, AMBA 3 AXI
LPDDR5X Synthesizable Transactor
- Supports 100% of LPDDR5X protocol draft JEDEC specification and JESD209-5B specification.
- Supports all the LPDDR5X commands as per the specs.
- Supports device density up to 32GB.
- Supports X8 and X16 device modes.
LPDDR5 Synthesizable Transactor
- Supports 100% of LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B.
- Supports all the LPDDR5 commands as per the specs
- Supports device density up to 32GB
- Supports X8 and X16 device modes
LPDDR5 DFI Synthesizable Transactor
- Compliant with DFI version 5.0 Specifications.
- Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
- Supports for Read data bus inversion.
- Supports for Write data bus inversion.
LPDDR5 DFI Verification IP
- Compliant with DFI version 5.0 Specifications.
- Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5, JESD209-5A and LPDDR5X(Draft).
- Supports for Read data bus inversion.
- Supports for Write data bus inversion.