LPDDR5X/5/4X/4 Memory Controller IP

Overview

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.

OMC – LPDDR5X/5/4X/4 Memory Controller is a small & highly configurable IP. It provides high performance through advanced memory controller design based on a proprietary out-of-order scheduling algorithm and high-speed implementation technique. Demand for more DRAM bandwidth is getting stronger than ever in a quest to improve user experiences (e.g., higher image resolution). Given the limited amount of physically available DRAM bandwidth, highly efficient memory controller IP is becoming a very critical issue everywhere. With our OMC – LPDDR5x/5/4x/4 Memory Controller, SoCs can save a significant amount of area & power consumption and meet next-generation SoC’s DRAM bandwidth requirements.

Key Features

  • Compliant with JEDEC standard for LPDDR5X/5/4X/4
  • DRAM rank of up to 4
  • Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
  • Support for dynamic DRAM frequency scaling
  • In-line ECC and Side-band ECC (SECDED)
  • Address region-based security control support
  • Automated low-power control of DRAM devices
  • Flexible refresh control (4 options)
  • Support DFI 5.0 Specification Compliant
  • Priority per request based on AXI QoS signal
  • The proprietary out-of-order scheduling algorithm
  • Ultra-low power consumption with HW-controlled dynamic DRAM frequency scaling
  • Automatically handles training activities required for frequency change
  • Muti-port master interface (optional)

Benefits

  • Intensive utilization using a proprietary out-of-order scheduling algorithm
  • Extremely low latency using a latency-aware algorithm. Safety & Security
  • Reliability using ECC and Security Firewall
  • Highly PPA based on a proprietary architecture
  • Active QoS control combined with ORBIT™ interconnect (OIC) for maximum performance & flexibility.

Block Diagram

LPDDR5X/5/4X/4 Memory Controller IP Block Diagram

Applications

  • Automotive
  • Application Processors
  • Digital Baseband Modems
  • Set-Top-Box
  • Digital TV
  • OTT
  • Surveillance
  • IoT, Enterprise
  • SSD Controllers

Deliverables

  • OMC is packaged with the following items for all eligible companies:
    • IP core RTL
    • Standalone Simulation Environment
    • Management SW
    • IP Documentation

Technical Specifications

Maturity
Silicon Proven & Market Proven
Availability
Now
×
Semiconductor IP