Serdes IP

Compare 185 Serdes IP from 32 vendors (1 - 10)

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- Layout for wirebond packaging
- Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
1-112Gbps Integrated Laser Driver and Optical SerDes
- Optical Optimization:
- Integrated laser driver
- RX front-end architected for optical signaling
- Non-linear DSP equalization that corrects for both static and dynamic nonlinearity components.
1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS)
- Most Likely Sequence Detector(MLSD)
- High speed A/D
- Sub-sampling clock multiplier
- Master Controller
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)
- High speed A/D
- Sub-sampling clock multiplier
- Master controller
224G-LR SerDes PHY enables 1.6T and 800G networks
- TSMC 3nm process
- Supports full-duplex 1.25 to 225Gbps data rates
- Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
112G-ELR PAM4 SerDes PHY
- Interoperability
- Maximize beach front bandwidth
- Layout flexibility