Multi-Protocol PHY IP
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Multi-Protocol PHY IP
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32
Multi-Protocol PHY IP
from 5 vendors
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MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2.
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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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10Gbps Multi-Protocol PHY IP
- Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
- High-performance decision feedback equalization and adaptive CTLE
- Available in X1 through X10 lane configurations
- Bifurcation and inverse bifurcation support
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MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
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SerialLite PHY with PCS
- Integrated PCS Layer
- Low power & area
- Test Silicon
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MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
- Backward compatible with MIPI® Specification for D-PHY Version 1.1
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224G Ethernet PHY in TSMC (N3E)
- Optimized for performance, power, and area
- Includes one, two, or four full-duplex PAM-4/6 transceivers (transmit and receive functions)
- Supports IEEE and OIF-CEI-224G standards
- Includes auto-negotiation and link training capabilities
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32G PHY in TSMC (N3A) for Automotive
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
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32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P)
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces