MIPI Controller IP for TSMC

Compare 50 MIPI Controller IP for TSMC from 5 vendors (1 - 10)

LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
- The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
- The polarity of differential signals for each data lane can be controlled.
MIPI D-PHY IP 4.5Gbps in TSMC N7
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Alliance Specification for D-PHY Version 2.1
MIPI D-PHY CSI-2 RX+ (Receiver) IP in UMC 40ULP
- Consists of 1 Clock lane and 4 Data lanes.
- Supports MIPI Alliance Specification for D-PHY Version 2.1
- Supports both high speed and low-power modes.
MIPI D-PHY Universal IP in TSMC 55LP
- Consists of 1 Clock lane and up to 4 Data lanes.
- Supports MIPI® Alliance Specification for D-PHY Version 1.1.
- Supports both high speed and low-power modes.
- 80 Mbps to 1.5 Gbps data rate in high speed mode.
MIPI M-PHY G4 Designed For TSMC 28nm HPC+
- Compliant to MIPI Alliance Standard for M-PHY specification Version 4.1
- Supports M-PHY Type-I system
- Support for Clock and Data Recovery Options
MIPI D-PHY Universal IP in TSMC 40LP-eF
- Consists of 1 Clock lane and up to 4 Data lanes.
- Supports MIPI® Alliance Specification for D-PHYSM Version 1.1.
MIPI D-PHY Universal IP in TSMC 40ULP
- Consists of 1 Clock lane and up to 2 Data lanes.
- Supports MIPI® Alliance Specification for D-PHYSM Version 1.1.
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2.
MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes