IP Catalog > Foundries > UMC > Interface IP > Interconnect IP > MIPI IP

MIPI IP for UMC

Welcome to the ultimate MIPI IP for UMC hub! Explore our vast directory of MIPI IP for UMC
All offers in MIPI IP for UMC
Filter
Filter

Login required.

Sign in

Search (52)
Compare 52 MIPI IP for UMC from 9 vendors (1 - 10)
  • MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI Specification for D-PHY Version 1.2
    • Supports MIPI Specification for C-PHY Version 1.0
    Block Diagram -- MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
  • MIPI D-PHY Universal IP in UMC 40LP
    • Consists of 1 Clock lane and up to 4 Data lanes
    • Supports the MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    Block Diagram -- MIPI D-PHY Universal IP in UMC 40LP
  • MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
    • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
    • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
    • Burst mode CDR with short sync length (< 16SI)
    • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
    Block Diagram -- MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
  • MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
  • MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
  • MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    Block Diagram -- MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
  • MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    • Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
    • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
    Block Diagram -- MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
  • MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
  • MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
  • MIPI M-PHY Compliant (HS-G2) IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports all HS modes (GEAR 1-2)
    Block Diagram -- MIPI M-PHY Compliant (HS-G2) IP
×
Semiconductor IP