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Cipher Accelerator IP for TSMC

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Compare 11 Cipher Accelerator IP for TSMC from 1 vendors (1 - 10)
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  • 7nm
  • ChaCha20 Accelerators
    • Wide bus interface (512-bit data, 256-bit keys) or 32-bit register interface
    • Key sizes: 128 and 256 bits
    • Includes key scheduling hardware
    • Feedback mode CTR. 

    Block Diagram -- ChaCha20 Accelerators
  • High speed low latency AES-GCM pipeline, 100Gbps
    • Silicon-proven implementation
    • Fast and easy to integrate into SoCs
    • Flexible layered design
    • World-class technical support
    Block Diagram -- High speed low latency AES-GCM pipeline, 100Gbps
  • AES XTS/GCM Accelerators
    • Wide bus interface
    • Basic AES encrypt and decrypt operations
    • Key sizes: 128, 192 and 256 bits
    • Key scheduling in hardware, allowing key, key size and 
direction changes every 13/15/17 clocks with zero impact 
on throughput
    • Hardware reverse (decrypt) key generation
    Block Diagram -- AES XTS/GCM Accelerators
  • 3GPP Kasumi Accelerators
    • Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
    • Includes key scheduling hardware.
    • Modes Kasumi
    • Algorithms f8 and f9.
    • Fully synchronous design.
    • Low Speed, High Speed versions.
    Block Diagram -- 3GPP Kasumi Accelerators
  • AES “All Modes” Accelerators
    • 32-bit register interface
    • Key sizes: 128, 192 and 256 bits
    • Includes key scheduling hardware
    • Feedback modes: ECB, CBC, CTR, OFB-128, 
CFB-128
    • Protocol modes: CCM, GCM, CMAC and XCBC-MAC
    Block Diagram -- AES “All Modes” Accelerators
  • AES Key Wrap Accelerators
    • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
    • Key/KEK sizes: 128, 192 and 256 bits
    • Includes key scheduling hardware
    • Supported modes: NIST AES Key Wrap
    • Memory interface for key, intermediate and result data storage up to 4096 bits 
(Maximum supported input data block size is 512 bytes) 

    Block Diagram -- AES Key Wrap Accelerators
  • 3GPP SNOW 3G Accelerators
    • Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface
    • Includes key scheduling hardware
    • Supported modes: UEA2, UIA2, 128-EEA1 and 128-EIA1
    • Fully synchronous design
    • Low Speed, High Speed versions
    Block Diagram -- 3GPP SNOW 3G Accelerators
  • AES ECB/CBC/CTR Accelerators
    • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
    • Key sizes: 128, 192 and 256 bits
    • Includes key scheduling hardware
    • Feedback modes: ECB, CBC, CTR, OFB (128 bit), 
CFB (1, 8 and 128 bit)
    • Fully synchronous design
    Block Diagram -- AES ECB/CBC/CTR Accelerators
  • ARC4 Stream Cipher Accelerators
    • Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface
    • Key sizes: 40 and 128 bits
    • Fully synchronous design
    Block Diagram -- ARC4 Stream Cipher Accelerators
  • AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
    • EXAMPLE CONFIGURATIONS
    • The SafeXcel-IP-63 has a scalable number of processing pipes and channels. It is available in different configurations, suitable for different applications to meet different gate count and throughput objectives.
    • • EIP-63a-c17-r
    • o single pipe, 17 channels, register based (no memories)
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