Video Interface IP for TSMC
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Video Interface IP
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5
Video Interface IP
for TSMC
from 2 vendors
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5)
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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V-By-One PHY & Controller (Tx+ Rx)
- Area: 1.224mm2 (1440um x 850um) including IO and ESD
- Compliant with V-By-One HS 1.4 standard
- Support 1/2/4/8-lane configuration
- Support 3/4/5-byte mode
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Video-by-One Transmitter IP_8ch
- Area: 0.98mm2 (1400um x 700um) including IO and ESD
- Compliant with V-By-One HS 1.4 standard
- Support 1/2/4/8-lane configuration
- Support 3/4/5-byte mode
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Video-by-One Receiver IP_16ch
- Compliant with V-by-One HS Standard Version 1.4
- Supports 1/2/4/8/16-lane configuration
- Supports 3/4/5-byte mode
- Supports data rate up to 4Gbps per lane
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V-By-One Receiver_8ch
- Area: 1.224mm2 (1440um x 850um) including IO and ESD
- Compliant with V-By-One HS 1.4 standard
- Support 1/2/4/8-lane configuration
- Support 3/4/5-byte mode