PCI Express Phy IP for TSMC
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PCI Express Phy IP
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PCI Express Phy IP
for TSMC
from 11 vendors
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PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
- Fully compliant with PCI Express Base 5.0 electrical specifications
- Compliant with PIPE5.2 (PCIe) specification
- Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
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PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
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PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
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High Performance, Low Latency PCIe Gen5 PHY
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
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PCI Express Gen 1/2/3/4 Phy
- TSMC advanced 16 nm FFC CMOS process
- Available in 1X, 4X, 8X, and 16X configuration
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PCI Express Gen 1/Gen 2 Phy
- 2.5/5.0 Gbps per lane interface optimized for PCI Express applications
- Conforms to PCI Express Specification 1.0a, 1.1 and 2.0
- PIPE compliant parallel interface
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PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
- Spread-spectrum clocking (SSC)
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USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- Compatible with PCIe/USB3/SATA base Specification
- Fully compatible with PIPE3.1 interface specification
- Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
- Support 16-bit or 32-bit parallel interface when encode/decode enabled
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PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)