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MIPI M-PHY IP for TSMC

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Compare 15 MIPI M-PHY IP for TSMC from 7 vendors (1 - 10)
  • MIPI M-PHY G4 Designed For TSMC 28nm HPC+
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 4.1
    • Supports M-PHY Type-I system
    • Support for Clock and Data Recovery Options
    Block Diagram -- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
  • MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
    • Supports MIPI® Alliance Specification for M- PHY® Version 4.1.
    • Dual-simplex point-to-point interface with ultra-low voltage differential signaling.
    • Slew-rate control for EMI reduction.
    Block Diagram -- MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
  • MIPI 4.1 M-PHY HS Gear 4
    • Supports high speed data transfer G4A/B and backward compatible
    • Multi-lane compatible
    • Supports 4 reference clocks as per MIPI 4.1 specification
    Block Diagram -- MIPI 4.1 M-PHY HS Gear 4
  • MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+
    • RX:DFE+CTLE, TX:2-tap FFE
    • Max. Channel Loss:~14dB @6GHz Nyquist
    • Low operation current and low standby current
    Block Diagram -- MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+
  • MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
    • Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
    • Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
    • Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
    • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
    Block Diagram -- MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
  • MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+
    • Compliant with M-PHY Spec 3.0
    • Support HS-MODE Gear3(A/B) with data rate up to 5.8Gb/s, and backward compatible
    • Support LS-MODE PWM-G1 to PWM-G4 with data rate up to 72Mb/s
    • Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec
    Block Diagram -- MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+
  • MIPI M-PHY in TSMC 65LP
    • Supports the MIPI Standard for M-PHY, Draft Specification v0.90.00-r02 and DigRF v4 V1.10.00.0.04
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports HS mode (GEAR 1-2, A & B)
    Block Diagram -- MIPI M-PHY in TSMC 65LP
  • MIPI M-PHY DigRF Compliant IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.00- r02 and DigRF v4 V1.10.00.0.04
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports HS mode (GEAR 1-2, A & B)
    Block Diagram -- MIPI M-PHY DigRF Compliant IP
  • MIPI M-PHY Compliant (HS-G2) IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports all HS modes (GEAR 1-2)
    Block Diagram -- MIPI M-PHY Compliant (HS-G2) IP
  • MIPI PLL
    • All output programmable dividers produce 50% duty cycle for both even and odd divisors
    • High performance, highly programmable MIPI Pixel PLL
    • Digital CMOS process
    • Low power dissipation
    Block Diagram -- MIPI PLL
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