USB IP for SMIC

Compare 33 USB IP for SMIC from 7 vendors (1 - 10)

USB1.1 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB2.0 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB2.0 build-in clock PHY, SMIC 40LL, type-C
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB 2.0 nanoPHY in SMIC (65nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Low power: <100mW (during HS packet transmission)
- Small area: ~ 0.6mm2
- High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
USB 2.0 femtoPHY in SMIC (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
USB3.2 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
USB2.0 PHY & Controller
- Compliant with USB Specification Revision 2.0, 1.1
- Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
- Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
- Supports low latency hub mode with 40-bit time round trip delay
USB2.0 OTG PHY
- Compliant with USB Specification Revision 2.0, 1.1
- Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
- Compliant with OTG Supplement to the USB Specification Revision 2.0
- Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
USB3.1/3.0 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
Type-C PHY
- Area: 1.92mm2 (1600um x 1200um) including IO and ESD
- Note: The area parameters are for reference only. Please refer to the final LEF file for the actual value.
- Compliant with DP1.2 and USB3.0 specifications
- Support DP 2/4-lane configuration