MIPI D-PHY IP for SMIC
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MIPI D-PHY IP
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28
MIPI D-PHY IP
for SMIC
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MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
- SMIC 130nm
- Consists of 1 Clock lane and 4 Data lanes
- Supporting the MIPI Standard 1.1 for D-PHY
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MIPI D-PHY CSI-2 RX (Receiver) IP
- Consists of 1 Clock lane and 2 Data lanes
- Complies with MIPI Standard 1.0 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1Gbps data rate in high speed mode
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MIPI PLL
- All output programmable dividers produce 50% duty cycle for both even and odd divisors
- High performance, highly programmable MIPI Pixel PLL
- Digital CMOS process
- Low power dissipation
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MIPI D-PHY Universal IP
- Complies with MIPI Standard for D-PHY V1.0
- Point-to-point differential interface supporting multiple data lanes and a clock lane
- Supports both high speed and low-power modes
- Data lanes support both bidirectional and unidirectional modes
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MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Bidirectional 2 Lanes in SMIC (40nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes