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MIPI D-PHY IP for SMIC

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Compare 35 MIPI D-PHY IP for SMIC from 7 vendors (1 - 10)
  • MIPI DPHY-RX

    • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps

    • Silicon proven in GlobalFoundries 22FDX process

    • Compliant to the MIPI D-PHY spec v1.2

    • Lane type:1 clock + 4 data(D0 is bi-dir)

    • Support for DPHY Ultra Low Power State

    Block Diagram -- MIPI DPHY-RX
  • MIPI DPHY-TX - GlobalFoundries 22FDX process
    • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
    • Silicon proven in GlobalFoundries 22FDX process
    • Compliant to the MIPI D-PHY spec v1.2
    • Support HiSPi-SLVS TX compatible mode
    Block Diagram -- MIPI DPHY-TX - GlobalFoundries 22FDX process
  • MIPI DPHY
    • Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC
    • Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)
    • Lane type:1 clock + 4 data, bi-directional
    • Built-in self test function
    Block Diagram -- MIPI DPHY
  • MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
    • SMIC 130nm
    • Consists of 1 Clock lane and 4 Data lanes
    • Supporting the MIPI Standard 1.1 for D-PHY
    Block Diagram -- MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
  • MIPI DPHY v1.2 Tx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 Tx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
  • MIPI DPHY v1.2 Rx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 Rx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
  • MIPI DPHY Gen2 Bidirectional 4 Lanes - SMIC 28HKMG 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY Gen2 Bidirectional 4 Lanes - SMIC 28HKMG 1.8V, North/South Poly Orientation
  • MIPI D-PHY CSI-2 RX (Receiver) IP
    • Consists of 1 Clock lane and 2 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY CSI-2 RX (Receiver) IP
  • MIPI PLL
    • All output programmable dividers produce 50% duty cycle for both even and odd divisors
    • High performance, highly programmable MIPI Pixel PLL
    • Digital CMOS process
    • Low power dissipation
    Block Diagram -- MIPI PLL
  • MIPI D-PHY Universal IP
    • Complies with MIPI Standard for D-PHY V1.0
    • Point-to-point differential interface supporting multiple data lanes and a clock lane
    • Supports both high speed and low-power modes
    • Data lanes support both bidirectional and unidirectional modes
    Block Diagram -- MIPI D-PHY Universal IP
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