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USB IP for Samsung

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Compare 43 USB IP for Samsung from 5 vendors (1 - 10)
  • USB3.0 PHY
    • Silicon proven in 22, 28, Global Foundries and Samsung
    • Spread Spectrum clock (SSC) and data scrambling to minimize EMI
    • Supports 16-bit 250-MHz , and 32-bit 125M PIPE interface
    • Multiple loopback and compliance test modes
    Block Diagram -- USB3.0 PHY
  • USB2.0 PHY
    • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, GlobalFoundries and Samsung
    • Low power dissipation while active, idle, or suspend
    • Compliant with the USB Spec Rev2.0/s
    • Compliant with the UTMI+ Spec Rev1.0 Level3
    Block Diagram -- USB2.0 PHY
  • USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
    • The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
    • It supports the USB3.0 5Gbps Super-Speed mode and backward compatibles with the USB2.0 480Mbps High-Speed, 12Mbps Full-Speed, and 1.5Mbps Low-Speed modes
    • The USB 3.0 PHY interface complies with PHY Interface for PCI Express and USB3.0 Architectures specification (PIPE 3.0) and the USB2.0 PHY interface complies with the UTMI v1.05 specification.
       
    Block Diagram -- USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
  • USB 2.0 femtoPHY SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - SS SF4X x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SS SF4X x1, North/South (vertical) poly orientation
  • AP1 USB 2.0 femtoPHY - SS 8LPU18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- AP1 USB 2.0 femtoPHY - SS 8LPU18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - Samsung 8LPP18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - Samsung 8LPP18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - Samsung 7LPP18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - Samsung 7LPP18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - Samsung 14LPP18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - Samsung 14LPP18 x1, OTG, North/South (vertical) poly orientation
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