MIPI PHY IP for Samsung

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Silicon IP (31)

Compare 31 MIPI PHY IP for Samsung from 6 vendors (1 - 10)

MIPI M-PHY G5 Type 1 2Tx2Rx - SS SF5A 1.2V, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
MIPI M-PHY G5 Type 1 2Tx2Rx - SS SF4X 1.2V, North/South Poly Orientation
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
MIPI M-PHY G4 Type 1 2Tx2Rx - SS 8LPU 1.8V, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 1
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
MIPI DPHY v1.2 TX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY v1.2 RX 2 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY v1.2 TX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY v1.2 RX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY v1.2 RX 2 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY
- Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC
- Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)
- Lane type:1 clock + 4 data, bi-directional
- Built-in self test function
MIPI DPHY-RX
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Lane type:1 clock + 4 data(D0 is bi-dir)
- Support for DPHY Ultra Low Power State