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PUF
- Root of trust, unclonable, chip dependent ID with unique static and dynamic signature behavior in each chip
- Process dependent, fully invisible, root of trust
- Support 0.18um, 0.13um, 55nm, 40nm, 28nm, 14nm
- Small Area: 0.02mm2 (140um x 140um) @SMIC 55nm
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DP/eDP1.4/1.2 TX PHY&controller
- Area: 0.75mm2 with pixel PLL and 0.63mm2 without pixel PLL including IO and ESD
- Compliant with DP1.4 and eDP1.4specification
- Typical 27MHz reference clock
- Supports 1/2/4-lane configuration
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DP/eDP1.4/1.2 RX PHY
- Compliant with DP1.4 and eDP1.4 specifications
- Supports 1/2/4-lane configuration
- Up to 8.1Gbps per data lane
- Typical 24MHz or 27MHz reference clock
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HSIC PHY
- Consumes <90mW during data transfer
- Consumes <50uW when not transferring data
- Uses standard chip digital and IO supplies
- Low pin count