Multi-Protocol PHY IP for GLOBALFOUNDRIES
Welcome to the ultimate Multi-Protocol PHY IP for GLOBALFOUNDRIES hub! Explore our vast directory of Multi-Protocol PHY IP for GLOBALFOUNDRIES
All offers in
Multi-Protocol PHY IP
for GLOBALFOUNDRIES
Filter
Compare
4
Multi-Protocol PHY IP
for GLOBALFOUNDRIES
from 2 vendors
(1
-
4)
-
SerialLite PHY with PCS
- Integrated PCS Layer
- Low power & area
- Test Silicon
-
28G LR Ethernet PHY in GF (12nm)
- Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
-
25G PHY in GF (14nm, 12nm)
- Includes one, two or four full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
-
25G Ethernet PHY in GF (14nm)
- Includes one, two or four full-duplex transceivers (transmit and receive functions)
- Supports back channel initialization, aggregation, bifurcation, and power management
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces