Video DAC (10bits, 300Msps)

Overview

Innosilicon Video DAC IP is designed for transmitting video signal from a video source device to a display device, which could be used for many analog video interfaces, such as Composite (CVBS), S-Video (Y/C) and Component (YPrPb and RGB) video interfaces.
Innosilicon Video DAC IP consists of the digital logic and the physical layer. The digital logic receives the video and clock signals from controller. It outputs these data to physical layer for further process.
The physical layer contains one or multiple current-steering DACs and bias circuit. Each DAC receives 10-bit parallel input data and converts the digital data to analog current output. The output current is programmable and maximum output current is 34.7mA, which results in a 1.3V voltage swing on typical 37.5? resistance load (double 75? termination). The update rate is up to 300MHz. The bias circuit generates voltage and current reference.
Innosilicon Video DAC IP offers reliable implementation for analog video interface, which can be integrated in the SOC used in multimedia device.

Key Features

  • Area: 0.232mm2 (400um x 580um) including IO and ESD
    • Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.
  • 10-bit 1-channel current-steering DAC
  • Up to 300MHz update rate
  • Support single-ended or differential output
  • Programmable current output range: 0~34.7mA
  • 56dBc SFDR @ Iout = 18.7mA, fclk = 300MHz and fout = 2MHz
  • 53dBc SFDR @ Iout = 26.7mA, fclk = 300MHz and fout = 2MHz
  • DNL< 2LSB, INL< 4LSB
  • Support cable detection
  • Support BIST logic
  • APB slave interface for internal register access
  • Built-in bandgap reference

Benefits

  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process

Deliverables

  • Databook and detailed physical implementation guides
  • Complete set of timing models
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • Layout vs. Schematic (LVS) report
  • GDSII database for foundry merge

Technical Specifications

Foundry, Node
Samsung 14/10/8nm, SMIC 55/40/28/14nm, TSMC 40/28/22/16/12nm, GF 55/28nm, HLMC 40/28nm
GLOBALFOUNDRIES
In Production: 28nm SLP , 55nm LPX
Silicon Proven: 28nm SLP , 55nm LPX
SMIC
In Production: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Samsung
In Production: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm
TSMC
In Production: 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP
Silicon Proven: 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP
UMC
In Production: 22nm , 40nm
Silicon Proven: 22nm , 40nm
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Semiconductor IP