UCIe IP Solutions

Overview

Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC links with streaming protocols.
The controller IP implements a RDI interface to the PHY and a FDI interface between the Die-to-Die Adapter layer and Protocol layer. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies and smooth link initialization and operation.
Synopsys UCIe Controller IP offers maximum performance, minimum latency and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection.
The flexible IP implementation targets single module or multi-module configurations, both for advanced and standard packages.
Synopsys UCIe Controller IP interoperates with Synopsys UCIe PHY to provide a complete, low-latency die-to-die interface solution that is optimized for bandwidth, power and area.

Benefits

Low Latency controller for UCIe-based die-to-die connectivity
Includes Die-to-Die Adapter layer and Protocol layer
Supports streaming, CXL and PCI Express protocols
Error detection and correction with optional CRC and retry functionality
Supports single module and multimodule UCIe configurations
Enables low latency NoC-to-NoC interface between two dies

Applications

Multi-Die SoC for:
High-performance computing and servers
Artificial intelligence / machine learning
Networking and infrastructure
Consumer and mobile

Deliverables

Executable .run installation file which includes: Custom-configured RTL source code (using Synopsys coreConsultant or coreAssembler tool); Synthesis (Design Compiler® and Fusion Compiler®), design-for-test, and power reduction scripts; Spyglass lint, CDC, RDC scripts (with Synopsys defined rules/goals); SystemVerilog verification environment containing, sample integrations of Synopsys UCIe Controller with Synopsys UCIe PHY and sample test cases
Documentation: Databook, User Guide, Installation Guide, and Release Notes
Synopsys coreConsultant/coreAssembler tools to support design flow management (for example generate RTL, Synthesis and Spyglass constraints, IPXACT, Simulation, and many others)

Technical Specifications

Maturity

Available on request

Availability

Available

Request Info