Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The CSI-2 specification is specially targets for Camera to Image application processor communication.
Innosilicon CSI-2 Receiver operates as a receiver of a CSI-2 link, which consists of a C/D combo PHY and a CSI-2 controller.
? The C/D combo PHY is used for the data transmission from a CSI-2 compliant camera sensor. In C/D-PHY, the link includes a High-Speed signaling for fast-data traffic and a low-power signaling mode for control purposes. Error information is generated for application layer to do further operation.
? The CSI-2 Receiver Controller works as a protocol layer between application layer and physical layer. It implements all three layers defined by CSI-2 Specifications, including Pixel Packing, Low Level Protocol, and Lane Management.
MIPI C/D-PHY CSI-2 RX IP
Overview
Key Features
- Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), V2.0
- Compliant with MIPI Alliance Standard for C-PHY Specifications V1.1
- Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
- HS, LP and ULPS modes supported
- The data transfer rate ranges from 450Msps to 2.5Gsps per trio (C-PHY)
- The data transfer rate ranges from 400Mbps to 2.5Gbps per lane (D-PHY)
- Implements all three CSI-2 MIPI Layers (Pixel/Byte Packing Layer, Low Level Protocol and Lane Management)
- Asynchronous transfer at low power mode with a bit rate of 10Mbps on both C-PHY and D-PHY supported
- Unidirectional mode supported
- Support lane de-skew for D-PHY
- Support date type: RGB/YUV/RAW (Based on actual application scenarios)
- Error detection and correction supported
- Automatic termination control for HS and LP modes
Deliverables
- Databook and physical implementation guides Netlist (Spice format for LVS)
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- GDSII to Foundry IP Merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
SMIC 28/12nm
SMIC
In Production:
28nm
Silicon Proven: 28nm
Silicon Proven: 28nm
Related IPs
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- MIPI CSI-2 Receiver
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.