Master DLL
Overview
The INNOSILICON DLL PHY provides the low power and high-speed applications with robust timing and small silicon area. According to the reference clock, an accurate 0/90/180/270 phase clock with the same frequency as the reference clock can be generated. The DLL PHY components contain DLL specialized functional and utility DLL up to 800Mbps in SMIC 28nm, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any DLL application.
Key Features
- Core power supply: 0.9V
- Area: 0.0086mm2 (260.35um*33.08um)
- Reference clock frequency range from 200MHz to 800MHz
- Output clock phase:0/90/180/270
- Cycle to Cycle jitter(C2C): <=150ps
- Normal power consumption: <30mw
- Bypass power consumption: <2mw
Technical Specifications
Foundry, Node
SMIC 28nm
SMIC
In Production:
28nm
Silicon Proven: 28nm
Silicon Proven: 28nm