eMMC/SDIO/SD

Overview

INNOSILICON eMMC/SD/SDIO Combo IP solution consists of a host controller and PHY and supports eMMC/SD/SDIO devices. When connecting the eMMC device, the IP supports HS400, HS200, High-Speed DDR, High-Speed SDR, and legacy speed mode. When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes.
The IP is fully compliant with the following standards: JESD84-B51 eMMC5.1 specifications, SD3.01 specifications, and SDIO3.00 specifications.

Key Features

Compliant with eMMC5.1 specifications, up to 200MHz
Support HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
Support Enhanced Strobe in HS400
Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
Support DS, HS, SDR12, SDR25, SDR50, SDR104 and DDR50 speed mode
Support adjusting the CMD/CLK/DAT IO Driver Strength
Support power sequence-free operations
Support open drain applications
ESD protection for I/O signal
Support Built-In Self-Test
Support VDDQ 3.3V/1.8V

Applications

Mobile Devices
Digital Cameras and Camcorders
Gaming Consoles
Automotive Electronics
Industrial Applications
Medical Devices

Deliverables

Databook
Integration and Simulation Guide
Detailed physical implementation guides for the complete PHY
Library Exchange Format (LEF) file with pin size and locations
Gate-level netlist and Standard Delay Format (SDF)Timing file
Encrypted Verilog Models
Layout Versus Schematic (LVS) flattened netlist and report
Design Rule Check (DRC) report
GDSII database for foundry merge
Optional backend integration

Technical Specifications

Foundry, Node

SMIC 14nm, TSMC 28nm, HLMC 28nm

SMIC

Pre-Silicon: 14nm

TSMC

Pre-Silicon: 28nm HPC , 28nm HPCP , 28nm HPM

Request Info