DP1.4 TX PHY

Overview

Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications.
Innosilicon eDP TX PHY contains a digital logic and a physical layer.
? The digital logic receives video, audio, and auxiliary data from the controller and outputs these data to the physical layer for further process.
? The physical layer contains the main link, the AUX channel, PLL, and bias circuit.
? The main link contains 4 high speed data channels to transmit video and other stream data. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical AC-coupled connection. The data rate is up to 8.1Gbps per channel.
? The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device.
? The PLL generates the clocks required by data channels and the digital logic.
? The bias circuit generates voltage and current reference.

Key Features

Area: 0.75mm2 with pixel PLL and 0.63mm2 without pixel PLL including IO and ESD

Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.

Compliant with DP1.4 and eDP1.4specification
Typical 27MHz reference clock
Supports 1/2/4-lane configuration
Up to 8.1Gbps data rate per data channel
Supports 20-bit parallel input up to 405MHz for each data lane
Supports AUX channel working in 1MHz Manchester-II coding mode
Supports programmable output swing, termination, and pre-emphasis
Supports BIST logic
APB3.0 slave interface for internal register access
Built-in low jitter core PLL, bandgap reference, and optional pixel PLL

Benefits

Low power consumption
Fully customizable
Small area
Simple integration process
Available options include:

Test chips and test boards
FPGA integration support
Chip level integration

Deliverables

Databook and detailed physical implementation guides for the complete PHY
Library Exchange Format (LEF) file with pin size and locations
Gate-level netlist and Standard Delay Format (SDF) Timing file
Layout Versus Schematic (LVS) flattened netlist in spice format and report
Encrypted Verilog Models
GDSII database for foundry merge
Module integration guidelines
Silicon validation report (when available)
Evaluation board (when available)

Technical Specifications

Foundry, Node

HLMC 28nm, SMIC 28nm, TSMC 22/12/7/5nm

SMIC

In Production: 28nm
Silicon Proven: 28nm

TSMC

In Production: 5nm , 7nm , 12nm , 22nm
Silicon Proven: 5nm , 7nm , 12nm , 22nm

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