Bi-directional AMBA AHB/AHB bridge

Overview

The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any frequency ratio between the two interconnected buses.

Internally, the bridge consists of two uni-directional AHB to AHB bridges and additional logic to synchronize signals (other than AHB signals) crossing high-speed bus and low-speed bus clock domains.

A high-speed AMBA AHB bus hosting e.g. LEON3 CPUs and a external memory controller can be interconnected with a with a low-speed AHB bus hosting e.g. hosting slow communication IP-cores.

Key Features

AMBA AHB master and AHB slave interfaces
Bi-directional communication, allows masters on either bus side
Handles single and burst transfers in both directions
Internal FIFOs for data buffering
Implements SPLIT response to improve AMBA AHB bus utilization
Synchronous clock support, any frequency ratio
Compatible with AMBA-2.0

Benefits

The AHB/AHB Bridge provides the capability develop system-on-a-chip designs with multiple AMBA AHB buses, that can operate on different clock frequencies.

Deliverables

Source code
Synplify project file
VHDL test bench
Template design for LEON3 processor
FPGA evaluation board (optional)

Technical Specifications

Maturity

Production

Availability

Now

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