The Expedera Origin E2 is designed for Artificial Intelligence (AI) applications in power sensitive devices such as mobile phones and edge nodes. By using on-chip memory only, the E2 eliminates the requirement for external DRAM access, saving system power while increasing performance, reducing latency and shrinking system BOM costs. It is tunable for specific workloads to provide an optimal performance profile for unique application requirements.
Expedera's scalable tile-based design includes a single controller (SSP), and multiple matrix-math units (MMP), accumulators (PSM), vector engines (VSP) and memory to store the network. Specific configurations depend on unique application requirements. The unified compute pipeline architecture enables highly efficient hardware scheduling and advanced memory management to achieve unsurpassed end-to-end low-latency performance. The patented architecture is mathematically proven to utilize the least amount of memory for neural network (NN) execution. This minimizes die area, improves bandwidth, saves power, and maximizes performance.
AI accelerator (NPU) IP - 1 to 20 TOPS
Overview
Key Features
- 1 to 20 TOPS performance
- Performance efficient 18 TOPS/Watt
- Scalable performance from 2-9K MACS
- Capable of processing HD images on chip
- Advanced activation memory management
- Low latency
- Tunable for specific workloads
- Hardware scheduler for NN
- Processes model as trained, no need for software optimizations
- Use familiar open-source platforms like TFlite
Benefits
- Speedup AI inference performance dramatically
- Avoid system over-design and bloated system costs
- Lowers BOM costs
- Optimal performance for power sensitive applications
- Suitable for latency sensitive applications
- Increases performance for your most critical and common workloads
- No heavy software support burden
- Speeds deployment
- Best in class platform support
Block Diagram
Applications
- Smartphone
- Consumer Electronics
- AR/VR
- Handheld devices
Deliverables
- RTL -or- GDS
- Documentation
- SDK (TVM based)
Technical Specifications
Maturity
In production
Availability
Production
Related IPs
- AI accelerator (NPU) IP - 16 to 32 TOPS
- AI accelerator (NPU) IP - 32 to 128 TOPS
- AI Accelerator: Neural Network-specific Optimized 1 TOPS
- AI Accelerator (NPU) IP - 3.2 GOPS for Audio Applications
- NPU / AI accelerator with emphasis in LLM
- Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation