The 3.3V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and
analog power cells along with the necessary support cells to construct a complete pad ring by abutment. An included rail splitter allows
multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
3.3V Wide Ranging GPIO
Overview
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 16nm FFC
Maturity
Silicon Proven
Availability
Available Now
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