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Floating Point Unit (FPU) IP

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Compare 7 Floating Point Unit (FPU) IP from 7 vendors (1 - 7)
  • Additive White Gaussian Noise Generator
    • High precision AWGN Channel emulator.
    • Programmable Pseudo Random Generator(LFSR).
    • Programmable number of output bits.
    Block Diagram -- Additive White Gaussian Noise Generator
  • Parameterizable pipelined multiplier
    • Synthesizeable, technology-independent IP Core for FPGA/ASIC and SoC
    • Coded with SystemVerilog
    • Wrapped with AXI Stream interface
    • 16-bit Fixed-Point Representation/Operation
    • Suitable for DSP or Machine Learning Applications
    Block Diagram -- Parameterizable pipelined multiplier
  • High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
    • Design Flexibility
    • Portability
    • Ease of programmability
    Block Diagram -- High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
  • Single- and double-precision IEEE-754 floating-point unit
    • IEEE-754 compliant, supporting all rounding modes and exceptions
    • Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs, negate
    • Data formats: single and double precision (32- and 64-bit floats)
    • Fully pipelined, 3 clock cycles latency for all operations except divide and square-root
  • Powered by the Focus Algorithm. Transforms audio streams to HD quality audio.
    • SNR Increase
    • Improved Phase Alignment
    • Linear: 1 sample in, 1 sample out
  • Floating Point Megafunctions
    • Floating-point computation performance is typically a balanced combination of the frequency at which the operators run and the pipeline latency of the operator hardware. This product yields a measure of GFlop performance metric. When designing for maximum GFlop performance in an FPGA, the total number of operators that can be placed in an FPGA is vital. As such, you can parameterize the Altera floating-point megafunctions in many different ways to fine-tune GFlop performance (or, similarly, for other key metrics such as power and area) to meet the application-specific requirements. The configurable features include:
  • IEEE 754 Floating Point Coprocessor
    • User selectable precision
    • Fast Hardware execution of primary math functions
    • Full IEEE compliance in hardware
    • Smaller Fast mode only version with full IEEE compliance via software support
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