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SATA Controller IP

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Compare 68 SATA Controller IP from 18 vendors (1 - 10)
  • SATA-IP core - File system management without CPU
    • SATA IP core compliant with the Serial ATA specification revision 3.0 and work on AMD UltraScale and 7-Series device.
    • This IP core provide link layer. Design Gateway provide transport layer and 150MHz GTX physical layer design for 6.0Gbps SATA-III interface as reference design.
    • It can connect with SATA-III HDD directly without external PHY chip.
    Block Diagram -- SATA-IP core - File system management without CPU
  • SATA Verification IP
    • Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
    • Supports 1.5, 3 and 6 Gbps speeds.
    • Supports Port Multiplier Discovery and Enumeration.
    • Supports following interfaces
    Block Diagram -- SATA Verification IP
  • SATA Synthesizable Transactor
    • Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
    • Supports 1.5, 3 and 6 Gbps speeds.
    • Supports Port Multiplier Discovery and Enumeration.
    • Supports TBI interface with following bits
    Block Diagram -- SATA Synthesizable Transactor
  • SATA HOST CONTROLLER IIP
    • Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    Block Diagram -- SATA HOST CONTROLLER IIP
  • SATA 3.3 Verification IP
    • Compliant to SATA 3.3, PIPE and AHCI 1.3.1 Specification and backward Compatible to SATA 1.0 ,SATA 2.0 and SATA 3.2 specification.
    • Supports AHCI functionality on Host (HBA) side.
    • Supports complete functionality of Application, Command, Transport, Link and PHY Layer.
    • Configurable PIPE Interface width 8,16 or 32 bits.
    Block Diagram -- SATA 3.3 Verification IP
  • SATA 3 Controller IP
    • Simple AXI streaming TX and RX interface for application layer communication.
    • It supports Native Command Queuing and key primitives/FIS types from SATA specifications.
    • Compliant with Serial ATA 3.0 specification.
    • Supports data rates of 1.5/3/6 Gbit/s.
    Block Diagram -- SATA 3 Controller IP
  • NAND Flash Controller
    • The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips.
    • It is designed with scalability in mind and provides standard AXI interface for the ease of integration in SoC design.
    • The NFC has many configurable features to support the requirements for different NAND Flash applications.
    Block Diagram -- NAND Flash Controller
  • LDPC Encoder / Decoder
    • Support 1KB+/2KB+/4KB+ codeword size for one time configuration
    • Support code rate (CR) range 0.93~0.83(down to 0.71)
    • Support configurable throughput, ranges from 300MB/s to 16GB/s
    • Support hard-bit decode (HBD) and up to 6bit soft-bit decode (SBD)
    Block Diagram -- LDPC Encoder / Decoder
  • Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
    • High Throughput
    • Low Latency
    • Connects to SAPIS compliant serial ATA Phy
    Block Diagram -- Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
  • Serial ATA I/II Device Controller IP Core
    • The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices.
    • The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.
    Block Diagram -- Serial ATA I/II Device Controller IP Core
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