DDR4 IP
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20
DDR4 IP
from 7 vendors
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10)
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DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
- Compliant with JEDEC standard for LPDDR5/4/3, DDR4/3
- DRAM rank of up to 4
- Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
- Support for dynamic DRAM frequency scaling
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LPDDR4/3, DDR4/3 Memory Controller IP
- Compliant with JEDEC standards for LPDDR4/3, DDR4/3
- DRAM rank of up to 4
- Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
- Support for dynamic DRAM frequency scaling
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DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR PHY & DDR CONTROLLER IP
- DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
- LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
- Support speeds up to 4266Mbps.
- IP is split into 2 hard macros.
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DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
- Support x8/x16/x32 DRAM data bus configuration (programmable)
- Support Multi-Ranks DRAM configuration
- DDR base on DFI spec 4.0 compliant.
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DDR 4/3 Memory Controller IP - 2400MHz
- Support s DDR 4 /DDR3 SDRAM
- 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
- 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
- Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
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DDR4 Memory Controller
- Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
- Minimal latency achieved via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports half-rate and quarter-rate clock operation
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DDR4/3L PHY for TSMC
- Application optimized configurations for fast time to delivery and lower risk
- Memory controller interface complies with DFI standards up to 5.1
- Internal and external datapath loop-back modes
- Per-bit deskew on read and write datapath
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Denali High-Speed DDR PHY for TSMC 22ULP
- LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
- I/O pads with impedance calibration logic and data retention capability
- Optional clock gating available for low-power control
- Multiple PLLs for maximum system margin