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DDR4 PHY IP

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Compare 7 DDR4 PHY IP from 4 vendors (1 - 7)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
  • DDR PHY & DDR CONTROLLER IP
    • DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
    • LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
    • Support speeds up to 4266Mbps.
    • IP is split into 2 hard macros.
    Block Diagram -- DDR PHY & DDR CONTROLLER IP
  • DDR4/3L PHY for TSMC
    • Application optimized configurations for fast time to delivery and lower risk
    • Memory controller interface complies with DFI standards up to 5.1
    • Internal and external datapath loop-back modes
    • Per-bit deskew on read and write datapath
  • Denali High-Speed DDR PHY for TSMC 22ULP
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
    • DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • Built-in Gate Training, Read/Write Leveling, and VREF Training
    • Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
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