PCI Express Phy IP

Compare 89 PCI Express Phy IP from 22 vendors (1 - 10)

1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- High speed performance
- Low power architecture
- Robust training
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
- Fully compliant with PCI Express Base 5.0 electrical specifications
- Compliant with PIPE5.2 (PCIe) specification
- Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
High Performance, Low Latency PCIe Gen5 PHY
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
PCIe 6.0 PHY on 5nm
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
PCIe 4.0 PHY on 8nm
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
PCI Express 4.0 PHY
- Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
- Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer
- Supports 2.5GT/s and 5.0GT/s serial data transmission rate
- Supports 16-bit or 32-bit parallel interface
- Data and clock recovery from serial stream