PHY for PCIe 5.0 and CXL

Overview

The PHY IP for PCI Express^® (PCIe^®) 5.0 is a high-performance SerDes configurable to operate from 1.25Gbps to 32Gbps in NRZ mode. This state-of-the-art PHY is designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability. In addition, the SerDes IP features low data path latency and low power consumption, making it ideal for deployment in time-sensitive applications in high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), networking, and storage systems.

Key Features

Low-latency, long-reach, and low-power modes
Wide range of protocols that support networking, storage, and computing applications
Advanced equalization and clock-data-recovery to deliver unmatched channel loss handling performance and reliability
Eye Surf —provides convenient access to an integrated non-destructive real-time eye scope and BER bathtub curve to monitor the bit error rate (BER) and the link performance during live traffic
Comprehensive set of diagnostic and test features is embedded and easily accessible by the user to accelerate silicon bring-up and simplify troubleshooting
Extensive set of isolation, test modes, and loop-backs including APB and JTAG
Supports PIPE 5.2 standard
Built-in support for 1x16 to 16x1 modes of operation

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

Integration Views: Verilog behavioral model, GDSII, CDL, and power models
Synthesizable RTL
DFT-Verilog netlists with SS/FF, CTL, and BSDL
Reference Verilog testbenches used for generating SoC-level VCD ATE test patterns for PHY
IBIS-AMI kit

Technical Specifications

Foundry, Node

TSMC 5nm

Maturity

Silicon proven

TSMC

Silicon Proven: 5nm

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