Vendor: Cadence Design Systems, Inc. Category: Multi-Protocol PHY

PHY for PCIe 5.0 and CXL

The PHY IP for PCI Express® (PCIe®) 5.0 is a high-performance SerDes configurable to operate from 1.25Gbps to 32Gbps in NRZ mode.

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TSMC 5nm N5 Silicon Proven View all specifications

Overview

The PHY IP for PCI Express® (PCIe®) 5.0 is a high-performance SerDes configurable to operate from 1.25Gbps to 32Gbps in NRZ mode. This state-of-the-art PHY is designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability.  In addition, the SerDes IP features low data path latency and low power consumption, making it ideal for deployment in time-sensitive applications in high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), networking, and storage systems.

Key features

  • Low-latency, long-reach, and low-power modes
  • Wide range of protocols that support networking, storage, and computing applications
  • Advanced equalization and clock-data-recovery to deliver unmatched channel loss handling performance and reliability
  • Eye Surf —provides convenient access to an integrated non-destructive real-time eye scope and BER bathtub curve to monitor the bit error rate (BER) and the link performance during live traffic
  • Comprehensive set of diagnostic and test features is embedded and easily accessible by the user to accelerate silicon bring-up and simplify troubleshooting
  • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
  • Supports PIPE 5.2 standard
  • Built-in support for 1x16 to 16x1 modes of operation

Block Diagram

PHY for PCIe 5.0 and CXL block diagram

Applications

  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

What’s Included?

  • Integration Views: Verilog behavioral model, GDSII, CDL, and power models
  • Synthesizable RTL
  • DFT-Verilog netlists with SS/FF, CTL, and BSDL
  • Reference Verilog testbenches used for generating SoC-level VCD ATE test patterns for PHY
  • IBIS-AMI kit

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 5nm N5 Silicon Proven

Specifications

Identity

Part Number
PHY for PCIe 5.0 and CXL
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PHY for PCIe 5.0 and CXL?

PHY for PCIe 5.0 and CXL is a Multi-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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