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JESD204 IP

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Search (28)
Compare 28 JESD204 IP from 10 vendors (1 - 10)
  • JESD204D
    • Richly Featured
    • Easy to use
    • Solid
    • Silicon Agnostic
    Block Diagram -- JESD204D
  • JESD204C
    • Standard version: JESD204C, Dec 2017
    • Versions Available: Transmitter / Receiver
    • Silicon Agnostic: Targets ASIC, ASSP, FPGA
    Block Diagram -- JESD204C
  • JESD204B
    • Standard version: JESD204B.01, January 2012
    • Versions Available: Transmitter / Receiver
    • Silicon Agnostic: Targets ASIC, ASSP, FPGA
    Block Diagram -- JESD204B
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
    • Widest feature set available in market.
    • Scrambling and de-scrambling Included.
    • High performance transport layer support.
    • Build in test functions
    Block Diagram -- JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
  • JESD207 IP
    • Data path clock and data rate controlled by RFIC (configured by BBIC) up to 90 MHz and 180 MSps
    • Data width matched to baseband sample width – 10 or 12 bits
    • Raw data path interface transfer bandwidth up to 1.8 or 2.2 Gbps
    • Double data rate (DDR) source-synchronous data path transfer timing
    Block Diagram -- JESD207 IP
  • JESD204B IP Core
    • Subsets of JEDEC Standard No. 204B(JESD204B.01) July 2011
    • Rx core performs lane alignment based on Subclass 0 and Subclass 1
    • Rx core performs frame alignment detection / monitoring and octet reconstruction
    • Rx core performs user-enabled descrambling
    Block Diagram -- JESD204B IP Core
  • JESD204A IP Core
    • Compliant with JEDEC Standard No. 204A (JESD204A) April 2008
    • Rx core performs lane alignment buffering / detection / monitoring and correction
    • Rx core performs frame alignment detection / monitoring and octet reconstruction
    • Rx core performs user-enabled descrambling
    Block Diagram -- JESD204A IP Core
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 28HPC+
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B /204C PHY&MAC
    • X4/X8 Lane Mode, support up to 25Gbps (per lane)
    • Shared common PLL based architecture
    • Digitally-control-impedance termination resistors and On-chip resistance calibration
    • Configurable TX output differential voltage swing
  • JESD204C Transmitter and Receiver
    • With the addition of error correction and Detection(FEC, CRC), cutting-edge instrumentation and other applications can operate without any errors.
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