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DDR IP for UMC

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Compare 102 DDR IP for UMC from 5 vendors (1 - 10)
  • DDR4 multiPHY - UMC 28HPC18
    • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR4-2667
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
    Block Diagram -- DDR4 multiPHY - UMC 28HPC18
  • LPDDR4 multiPHY V2 - UMC 28HPC+18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - UMC 28HPC+18
  • DDR4 multiPHY in UMC (28nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR4 up to 2667 Mbps
    • Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
    • Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
  • Denali High-Speed DDR PHY for UMC
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • DDR4/3 Combo PHY & Controller
    • DDR4 and DDR3 modes & signaling, rates from 20Mbps up to 2133Mbps (DDR4) and 1866Mbps (DDR3), respectively
    • x16/x32/x64/x72 data path interface extendable
    • Independent read and write timing adjustments with auto calibration
    • Programmable write post-amble (0.5 tCK or 1.5 tCK)
  • DDR3/3L/2 Combo PHY & Controller
    • DDR3/3L/2 modes & signaling, rates from 20Mbps up to 1600Mbps (DDR3/3L) and 1066Mbps (DDR2), respectively
    • x16/x32/x64 data path interface extendable
    • 1.35V/1.5V/1.8V JEDEC IO standard, support 1.35V/1.5V/1.8V SSTL I/Os
    • Multiple drive strengths adjustable
  • DDR4/3/2 Combo PHY & Controller
    • DDR4/DDR3/DDR2 modes & signaling, rates from 100Mbps up to 2400Mbps
    • x16/x32/x72 data path interface extendable
    • 1.8V/1.5V SSTL & 1.2V POD JEDEC standard IO
    • Multiple drive strengths adjustable
  • DDR3/3L/2/LPDDR3/2 Combo PHY & Controller
    • LPDDR3/2 modes & signaling, rates from 20Mbps up to 2133Mbps (DDR3/3L), 1066Mbps (DDR2/LPDDR2) and 1600Mbps (LPDDR3) respectively
    • x16/x32/x64 data path interface extendable
    • 1.2V/1.35V/1.5V/1.8V JEDEC IO standard, support 1.2V POD_12 and 1.35V/1.5V/1.8V SSTL I/Os
    • Multiple drive strengths adjustable
  • DDR4/3/3L/LPDDR3 Combo PHY & Controller
    • DDR4 and DDR3/3L/LPDDR3 modes & signaling, rates from 20Mbps up to 2400Mbps (DDR4), 2133Mbps (DDR3) and 1866Mbps (LPDDR3), respectively
    • x16/x32/x64 data path interface extendable
    • 1.2V/1.35V/1.5V JEDEC IO standard, support 1.2V POD_12 and 1.35V/1.5V SSTL I/Os
    • Multiple drive strengths adjustable
  • DDR4/3/LPDDR4/3 Combo PHY & Controller
    • DDR4/3 and LPDDR4/4X/3 modes & signaling, rates from 20Mbps up to 2667Mbps (DDR4/LPDDR4/4X) and 2133Mbps (DDR3/LPDDR3), respectively
    • x16/x32 data path interface extendable
    • 1.2V/1.1V/1.5V JEDEC IO standard, support 1.5V SSTL, 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
    • Optional limited swing to VDDQ/3 in LPDDR4 mode
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