DDR3/3L/2/LPDDR3/2 Combo PHY & Controller

Overview

Key Features

• LPDDR3/2 modes & signaling, rates from 20Mbps up to 2133Mbps (DDR3/3L), 1066Mbps (DDR2/LPDDR2) and 1600Mbps (LPDDR3) respectively
• x16/x32/x64 data path interface extendable
• 1.2V/1.35V/1.5V/1.8V JEDEC IO standard, support 1.2V POD_12 and 1.35V/1.5V/1.8V SSTL I/Os
• Multiple drive strengths adjustable
• Independent read and write timing adjustments with auto calibration
• Low latency with programmable timings for secure data handling
• Per bit deskew support
• Supports point to point memory sub systems and multi-rank
• PVT compensation and timing calibration for all corner reliability
• At speed BIST, scan insertion
• Various power-down modes for low power including self-refresh support
• Low jitter with superior noise rejection
• APB Port register access interface
• Dual Row IO implementation and more
• Implemented using 0.9V RVT&LVT core devices and 1.8V gate oxide IO devices
• Supports both wire-bond and flip- chip packaging
• Wire-bond speed is package limited
• Support different DDRn type signal mapping for feasible PCB layout

Benefits

• Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
• Zero risk with robust ESD architecture
• Maintains self-refresh I/O drive state during VDD power down
• Extensive EDA tool support for various design automation flows
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
• DFI2.1/3.1 compliant memory controller interface
• Flexible pad ring configuration to adapt for various design and chip scenarios
• Integration with other INNOSILICON interface IP
• Takes full advantage of process power savings and speed capability
• Best in class low noise design to ensure best timing margin and signal integrity
• DFT functions to reduce test time and ensure high test coverage
• Several programmable PHY operating modes through simple register interface
• Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

• Verilog models
• LEF
• Place-and-route abstracts
• GDSII files
• LVS netlists
• Optional extracted HSPICE netlist for I/Os
• Data book, Application notes
• Silicon validation and ESD testing results
• Optional PCB reference design and Package Electrical Model
• Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications