Interconnect IP for Tower
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for Tower
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MIPI D-PHY CSI-2 RX (Receiver) IP
- Consists of 1 Clock lane and 2 Data lanes
- Complies with MIPI Standard 1.0 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1Gbps data rate in high speed mode
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MIPI PLL
- All output programmable dividers produce 50% duty cycle for both even and odd divisors
- High performance, highly programmable MIPI Pixel PLL
- Digital CMOS process
- Low power dissipation
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MIPI D-PHY Universal IP
- Complies with MIPI Standard for D-PHY V1.0
- Point-to-point differential interface supporting multiple data lanes and a clock lane
- Supports both high speed and low-power modes
- Data lanes support both bidirectional and unidirectional modes
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I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes:
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I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master only with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes: