UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
Overview
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
55nm
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