SWP Verification IP

Overview

SWP Verification IP is a smart way to verify the SWP component of a SOC or ASIC. The SmartDV's SWP Verification IP is fully compliant with standard ETSI TS 102 613 and ETSI TS 102 221 Specification. It supports all frame types such as ACT frame ,SHDLC and CLT frame. The SWP Verification IP monitor acts as powerful protocol-checker. SWP Verification IP includes an extensive test suite covering all possible scenarios. It can perform all protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. This way it detects violation of protocol completely.

SWP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SWP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with ETSI TS 102 613 and ETSI TS 102 221 Specification.
Complete SWP Clf/Uicc functionality.
Supports SWP interface between CLF and UICC
Supports different types of layers,

Physical layer
Data link layer
MAC layer
LLC layer

Supports contacts activation and deactivation
Supports ACT LLC, SHDLC LLC and CLT LLC
Support SHDLC LLC frame types,

I-Frames
S-Frames
U-Frames

Supports configurable timing functions.

Acknowledge time
Guarding/transmit time
Connection time

Supports CRC calculation
Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timings and protocol violations.
Supports constraints Randomization.
Status counters for various events on bus.
Callbacks in transmitter, receiver and monitor for user processing of data.
SWP Verification IP comes with complete test suite to test every feature of SWP specification.
Functional coverage for complete SWP features.

Benefits

Rich set of configuration parameters to control the functionality.
Faster testbench development and more complete verification of SWP designs.
Easy to use command interface simplifies testbench control and configuration of UICC and CLF.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SWP testcases.
Examples showing how to connect various components, and usage of UICC,CLF and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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