SWP Verification IP is a smart way to verify the SWP component of a SOC or ASIC. The SmartDV's SWP Verification IP is fully compliant with standard ETSI TS 102 613 and ETSI TS 102 221 Specification. It supports all frame types such as ACT frame ,SHDLC and CLT frame. The SWP Verification IP monitor acts as powerful protocol-checker. SWP Verification IP includes an extensive test suite covering all possible scenarios. It can perform all protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. This way it detects violation of protocol completely.
SWP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SWP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.