SPI/FRAM Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/SPANSION_FLASH Verification IP is fully compliant with SPI Block Guide V04.01 of the FRAM's FM25L512 512Kb Memory Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
SPI/FRAM Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SPI/FRAM Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.