RapidIO 2.0 PHY & Controller

Overview

The Innosilicon Serdes Combo PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for RapidIO. The PHY supports the RapidIO 1.25/2.5G/3.125Gbps/6.25Gbps physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer.

Key Features

One to Four independent 1.25/2.5/3.125Gbps per ports
Features as per RapidIO Specification revision v2.2
Precision low jitter master PLL and CDR loop
Supporting a 10 bit SerDes interface
100-ohm differential on-chip terminated drivers and receivers
Automatic impedance calibration
Multiple Built-in self test modes and test pattern generation
Near-end loopback for testability
Far-end loopback for testability
Proprietary low cap ESD structures
On-chip PRBS generation and verification controlled from external terminal

Benefits

As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
Small size
Low power
High ATE coverage
Simple integration
Flexible customization

Applications

Rapidio controller

Technical Specifications

Foundry, Node

Samsung 14/10/8nm, GF 55/22/14/12nm, SMIC 55/40/28/14nm, TSMC 55/40/22nm, UMC 55/40/28/22nm, HLMC 40nm

Maturity

Silicon proven and in volume production

Availability

now

GLOBALFOUNDRIES

In Production: 12nm , 14nm LPP , 22nm FDX , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 55nm LPX

SMIC

In Production: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL

Samsung

In Production: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm

TSMC

In Production: 22nm , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 22nm , 40nm G , 40nm LP , 55nm LP

UMC

In Production: 22nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm

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