RapidIO IP
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16
RapidIO IP
from 10 vendors
(1
-
10)
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RapidIO Controller with V4.1 Support
- Compliant to RapidIO Specifications revision 4.1
- Compliant with RapidIO Error Management
- Extension specification, Revision 4.1
- Implements Logical, Transport and Physical layers functions
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RapidIO to AXI Bridge (RAB)
- Compliant with RapidIO specification, Revision 4.0
- Compliant to AMBA AXI protocol v4
- Supports 32-bit or 38-bit addressing
- AXI PIO operation with configurable number of AXI Slaves
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A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- GPIO:
- I2C / SMBUS Open-Drain I/O:
- LVDS
- ANALOG
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A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- GPIO:
- I2C / SVID Open-Drain I/O:
- ANALOG
- OTP Programming Cell
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Serial RapidIO 2.1 Endpoint IP Core
- LatticeECP3 AMC Evaluation board
- Associated cables
- AMC interface card
- Demonstration bitstreams and files
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Serial RapidIO - Physical Layer Interface
- Supports High Speed 1x Mode (up to 2.5 Gbps)
- 8B/10B Encoding and Decoding
- Clock and Data Recovery (CDR)
- Lane Synchronization
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RapidIO PHY
- 4 Channel per Quad
- Shared Quad common PLL architecture
- Digitally-control-impedance termination resistors
- Configurable TX output differential voltage swing
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RapidIO 2.0 PHY & Controller
- One to Four independent 1.25/2.5/3.125Gbps per ports
- Features as per RapidIO Specification revision v2.2
- Precision low jitter master PLL and CDR loop
- Supporting a 10 bit SerDes interface
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RapidIO EndPoint Controller IP
- Compliant with RapidIO Interconnect 2.2 specification
- Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
- Supports high link utilization and low latency
- Supports efficient receive and transmit buffering scheme