The MIPI M-PHY Verification IP provides an effective & efficient way to verify the components interfacing with MIPI M-PHY interface of an IP or SoC. The MIPI M-PHY VIP is fully compliant with MIPI Alliance Specification for M-PHY Version 5.0. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
MIPI M-PHY Verification IP
Overview
Key Features
- Compliant to MIPI M-PHY Version 5.0
- Supports two SUB-LINKs with configurable number of LANEs in each
- Supports high speed and low speed modes for all modules
- Supports HS-BURST with all HS-GEARs, HS-G1 to HS-G3 in HS-MODE
- Supports both data rate series, RATE A-series and RATE B-series in HS-MODE
- Supports both Type-I MODULE and Type-II MODULE in LS-MODE
- Supports PWM-signaling with all PWM-Gears, PWM-G0 to PWM-G7 in Type-I MODULE of LS-MODE
- Supports NRZ-Signaling in Type-II MODULE of LS-MODE
- Supports RMMI protocol Interface at all interface widths
- Supports 8b10b encoding in M-TX and decoding in M-RX
- Supports bypassing of 8b10b encoding and decoding
- Supports callbacks in M-TX and M-RX
- Supports wide variety of Error Injections
- Supports real time exhaustive protocol checks in Monitor
- Supports assertions for protocol checks
- Supports coverage of various scenarios and state transitions
Block Diagram
