IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI D-PHY IP > MIPI D-PHY DSI TX IP

MIPI D-PHY DSI TX IP

Overview

Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The MIPI DSI specification is specifically targeted for the display communication in image application processors.
Innosilicon MIPI DSI Transmitter operates as a transmitter of a DSI link, which consists of a D-PHY and a DSI Controller.
? The Innosilicon D-PHY is used for the data transmission from a DSI controller. In D-PHY, the link includes a High-Speed signaling for fast-data traffic and a low-power signaling mode for control purposes. Error information is generated for application layer to do further operation.
? Innosilicon MIPI DSI Controller works as a protocol layer between application layer and physical layer, which mainly aims to pack and distribute the pixels to the physical layers. Innosilicon DSI Controller implements all three layers defined by MIPI DSI specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.

Key Features

  • Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI) V1.2
  • Compliant with MIPI® Alliance Standard for Display Bus Interface (DBI) V2.0
  • Compliant with MIPI® Alliance Standard for Display Pixel Interface (DPI) V2.0
  • Compliant with MIPI® Alliance Specification for D-PHY V1.2
  • Compliant with MIPI® Alliance Specification for Display Command Set (DCS) V1.3
  • Compliant with AMBA V3.0 APB Specification
  • Supports data type: RGB/YCbCr (based on actual application scenarios)
  • Data transfer rate up to 2.5Gbps per lane (D-PHY)
  • Supports DPI for video mode interface
  • Supports DBI for command mode interface
  • Type A Clocked E mode for DBI interfaces
  • Supports HS, LP and ULPS modes
  • Supports Skew-Calibration for D-PHY
  • Bidirectional communication and escape mode support through data lane 0
  • Automatic termination control for HS and LP modes
  • On die low jitter PLL integrated

Deliverables

  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
SMIC 40/14nm, Samsung 14nm, GF 14/12nm, TSMC 28/6/3nm
GLOBALFOUNDRIES
In Production: 12nm , 14nm LPP
Silicon Proven: 12nm , 14nm LPP
SMIC
In Production: 14nm , 40nm LL , 110nm G
Silicon Proven: 14nm , 40nm LL , 110nm G
Samsung
In Production: 14nm
Silicon Proven: 14nm
TSMC
In Production: 3nm , 6nm , 28nm HPC , 28nm HPCP , 28nm HPM
Silicon Proven: 3nm , 6nm , 28nm HPC , 28nm HPCP , 28nm HPM
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