The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC LPDDR2 SDRAM components in the market. The PHY components contain DDR specialized functional and utility I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. LPDDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes LPDDRn controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
LPDDR2 PHY & Controller
Overview
Key Features
- LPDDR2 modes & signaling, rates from 20Mbps up to 1066Mbps
- x16/x32/x64 data path interface extendable
- Multiple drive strengths adjustable
- Independent read and write timing adjustments with auto calibration
- Low latency with programmable timings for secure data handling
- Per bit deskew support
- Supports point to point memory sub systems and multi-rank
- PVT compensation and timing calibration for all corner reliability
- At speed BIST, scan insertion
- Various power-down modes for low power including self-refresh support
- Low jitter with superior noise rejection
- APB Port register access interface
- Dual Row IO implementation and more
- Implemented using 0.8V RVT&LVT core devices and 1.8V gate oxide IO devices
- Supports both wire-bond and flip- chip packaging
- Wire-bond speed is package limited
- Support different DDRn type signal mapping for feasible PCB layout
Benefits
- Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Maintains self-refresh I/O drive state during VDD power down
- Extensive EDA tool support for various design automation flows
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
- DFI2.1/3.1 compliant memory controller interface
- Flexible pad ring configuration to adapt for various design and chip scenarios
- Integration with other INNOSILICON interface IP
- Takes full advantage of process power savings and speed capability
- Best in class low noise design to ensure best timing margin and signal integrity
- DFT functions to reduce test time and ensure high test coverage
- Several programmable PHY operating modes through simple register interface
- Per Bit De-skew to improve composite data eye during read cycles at high speed
Deliverables
- Verilog models
- LEF
- Place-and-route abstracts
- GDSII files
- LVS netlists
- Optional extracted HSPICE netlist for I/Os
- Data book, Application notes
- Silicon validation and ESD testing results
- Optional PCB reference design and Package Electrical Model
- Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.
Technical Specifications
Foundry, Node
TSMC22nm, SMIC 28nm
Maturity
Silicon Proven
Availability
Available
SMIC
In Production:
28nm
Silicon Proven: 28nm
Silicon Proven: 28nm
TSMC
In Production:
22nm
Silicon Proven: 22nm
Silicon Proven: 22nm