DDR5 PHY IP

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Compare 477 DDR5 PHY IP from 19 vendors (1 - 10)
  • TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
    • Supports DDR5
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
  • LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
    • Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • x16 and x32 channel support
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
  • LPDDR5X/5/4X/4 combo PHY at 7nm
    • Unbeatable performance-driven and low-power-driven PPA
    • Ultra-low read/write latency with programmable PHY boundary timing
    • Channel equalization with FFE and DFE
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 7nm
  • GDDR6 Memory Controller IP
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- GDDR6 Memory Controller IP
  • LPDDR5X/5/4X/4 PHY IP for 12nm
    • Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 PHY IP for 12nm
  • DDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR PHY
  • DDR5/4 PHY for TSMC 7nm
    • Application optimized configurations for fast time to delivery and lower risk
    • Memory controller interface complies with DFI standards up to 5.0
    • Internal and external datapath loop-back modes
    • Per-bit deskew on read and write datapath
    Block Diagram -- DDR5/4 PHY for TSMC 7nm
  • DDR5/4 PHY for Samsung
    • Lowest latency for data-intensive applications
    • Highest data rates with detailed system guidelines
    Block Diagram -- DDR5/4 PHY for Samsung
  • DDR/LPDDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR/LPDDR PHY
  • Secure Digital I/O offerings
    • Secure Digital
    • Physical Features
    Block Diagram -- Secure Digital I/O offerings
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