HDCP Engine

Overview

Key Features

• Full HDCP1.x and HDCP2.x protocol support
  • Compliant with HDCP revision 1.4 and 2.2 specifications
  • Solid implementation of the HDCP robustness rules
  • Seamless integration with a wide range of EIP-114 Datapath modules, including HDMI1, HDMI2 and DisplayPort
  • HDCP software stack on embedded CPU
• True Random Number Generator
  • Hardware-based, Non-deterministic Random Number Generator
  • Implementation is based upon standard cells so no specific analog engineering is required
  • NIST SP 800-90 compliant
• Embedded Controller
  • Small low-power dedicated 32-bit processor
  • Autonomously runs one or more HDCP protocol stacks
  • Has exclusive access to HCDP secrets; ensures system security
• Asymmetric crypto algorithms
  • RSA-CRT - with a modulus length of 512 bits
  • RSA - with a modulus lengths of 1024 and 3072 bits
  • For the AKE part of the HDCP protocol
• Hash and HMAC algorithms
  • SHA-1 and SHA-256
  • HMAC-SHA-256
  • For the AKE part of the HDCP protocol
• NVM/OTP Interface
  • Generic NVM/OTP memory interface that allows easy integration of various non-volatile memory types
• Other modules
  • Advanced Interrupt Controller (AIC)
  • General Purpose Outputs (GPO)
  • Timers
• INTERFACES
  • I2C master and slave modules
  • 32-bit peripheral interface towards external EIP-114 datapath modules. Default interface type: APB
  • 32/16/8-bit generic NVM/OTP memory interface
• VERIFICATION
  • Set of test vectors for chip integration verification.
  • Integration test vectors in structured format.
  • Python / Verilog based verification environment.
  • 100% verification coverage.
• SYNTHESIS
  • Delivered with Synopsys Design Compiler TCL based synthesis scripts.
  • Technology independent script set verified with TSMC 65nm, 40nm and 28nm technologies.
  • Design is compliant with 16nm & 14nm FinFET technology.

Benefits

• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Applications

• In a content protection system, the EIP-116s forms the hardware-based security boundary wherein all secure parameters and cryptographic computations are managed during all the HDCP protocol phases from authentication of the connected devices up to and including the generation of the key stream. The EIP-116s is defined for being used in source and sink devices or in a combination of both (bridge/repeater devices).
• The EIP-116s module can be integrated into Application Processors, Multimedia Processors, SOCs for Set top Boxes, Graphics Processors, etc. The EIP-116s provides AES-128 key stream generation for commonly used interfaces, such as USB, WiFi and Ethernet. This also adapts to newly introduced wireless and wired interfaces like WiGig, WirelessHD, WHDI, DiiVA, etc. Although some of these interfaces require an additional interface specific cipher engine.

Deliverables

• Documentation
  • Hardware Reference Manual
  • Integration Manual
  • Verification Specification
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Configurations:
• EIP-116a-2i:
  • 2 I²C modules
  • 49k gates
  • up to 525 MHz
• EIP-116a-6i:
  • 6 I²C modules
  • 65k gates
  • up to 525 MHz

Technical Specifications