HBM3/3E PHY & Controller

Overview

Key Features

• Compliant with JEDEC Specification, up to 6400Mbps for HBM3, up to 9600Mbps for HBM3E
• Compliant with DFI 3.1 Specifications (dfi_clk_1x : WDQS = 1:4)
• supports up to 16 channels with 64 DQ-width + Optional DBI/ECC/SEV pin support/channel
• Supports command and DQ parity
• Supports per-AWORD de-skew tuning for command
• Supports bit-group de-skew tuning for data
• Supports CMD lane repair
• Supports DQ lane repair
• Supports automatic and soft command bus training
• Supports command and data IO driver strength adjustment
• Supports automatic and soft RX DQS training and bypass RX DQS control
• Supports automatic and soft WDQS2CK training and bypass WDQS2CK Control
• Supports automatic and soft read training
• Supports automatic and soft write training
• Supports bypass write and read trainings
• Supports automatic retraining mode and retraining bypass mode
• Supports ZQ calibration
• Supports Built-In Self-Test
• Supports boundary scan of pad
• Supports scan chain
• APB 3.0 interfaces to configure registers
• Supports IEEE1500 port for direct access to the memory stack and PHY using APB
• Supports HBM DRAM initialized by PHY

Deliverables

• Verilog models
• LEF
• Place-and-route abstracts
• GDSII files
• LVS netlists
• Databook, Application notes
• Silicon validation and ESD testing results
• Optional PCB reference design and Package Electrical Model
• Documentation

Technical Specifications