IP Catalog > USB 2.0 Hub

USB 2.0 Hub IP

Filter
Filter

Login required.

Sign in

Search (37)
Compare 37 IP from 13 vendors (1 - 10)
  • USB 2.0 Hub IP Core
    • The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.
    • The USB 2.0 Hub IP core consists of the Hub Controller, Hub Repeater, Transaction Translators, Routing Logic, and Downstream Ports.
    Block Diagram -- USB 2.0 Hub IP Core
  • USB 2.0 HUB (USB20HUB)
    • - Supports High speed, Full speed and Low speed peripheral devices
    • - Integrated Transaction Translator (TT)
    • - Supports individual port power switching
    • - Remote wakeup capable
  • USB 2.0 HUB - Hub PHY, 1upstream /4 downstream
    • Hub PHY, 1upstream /4 downstream
  • USB 2.0 Hub Controller
    • The USB 2.0 Hub core consists of Hub Controller, Repeater and Transaction Translator.
    • The Hub Controller provides the mechanism for host to hub communication.
    • Hub-specific status and control commands permit the host to configure a hub and to monitor and control its transaction translator individual downstream ports.
    Block Diagram -- USB 2.0 Hub Controller
  • USB 2.0 PHY IP core
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY IP core
  • USB 2.0 OTG IP Core
    • High speed support: 480 Mbit/s
    • Full speed support: 12 Mbit/s
    • USB 2.0 Compliant
    • High/Full speed support using 8/16 bit UTMI/ULPI interface
    Block Diagram -- USB 2.0 OTG IP Core
  • USB 2.0 Host IP Core
    • The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
    • The USB 2.0 Host IP supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.
    Block Diagram -- USB 2.0 Host IP Core
  • USB 2.0 Device IP Core
    • High speed support: 480 Mbit/s
    • Full speed support: 12 Mbit/s
    • USB 2.0 Compliant
    • High/Full speed support using 8/16 bit UTMI/ULPI interface
    Block Diagram -- USB 2.0 Device IP Core
  • High Speed Inter-CHIP USB 2.0 PHY
    • High-Speed 480Mbps data rate only
    • Source-synchronous serial interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- High Speed Inter-CHIP USB 2.0 PHY
  • USB 2.0 Device Controller IP
    • The USB 2.0 device controller can be configured to support all types of USB transfers – bulk, interrupt and isochronous. While operating in device mode, it can be dynamically configured to support a configurable number of endpoints, interfaces, alternate interfaces, and settings.
    • The USB 2.0 device controller can be configured to support any combination of USB 2.0 interface speeds – LS (1.5 Mbps), FS (12.0 Mbps), HS (480 Mbps). Sample combinations are LS only, FS only, HS only, LS and FS, and FS and HS.
    • The USB 2.0 device controller supports all low-power features of USB specifications, including suspend, remote wakeup and Link Power Management states – L1, L2.
    • The USB 2.0 device controller supports all test modes features, a requisite for obtaining USB-IF certification
    Block Diagram -- USB 2.0 Device Controller IP
×
Semiconductor IP