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eMMC IP

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Search (21)
Compare 21 eMMC IP from 7 vendors (1 - 10)
  • eMMC 5.1 Host Controller
    • Compliant with eMMC Specification Version 5.0
    • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
    Block Diagram -- eMMC 5.1 Host Controller
  • eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
    • Silicon proven, fully compliant core
    • Premier direct support from IP core designers
    • Easy-to-use industry standard test environment
    Block Diagram -- eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
  • SD/eMMC Host Controller
    • Supports selection between SD and eMMC
    • Supports CRC7 and CRC16 generation and verification on Hardware
    • Supports multiple block transfer
    Block Diagram -- SD/eMMC Host Controller
  • eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
    • • Suitable for Transmitter, Receiver, and Data Strobe pins
    • VCORE Pre driver voltage
    • VCCQ Post driver voltage
    • TJ Junction temperature
    Block Diagram -- eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
  • eMMC Device Controller
    • Compliant to the eMMC Electrical Standard 5.1A
    • Supports Backwards Compatible, High Speed SDR, High Speed DDR, HS200 and HS400 transfer modes
    • Host transfer rate of up to 400 MByte/s in HS400 mode
    Block Diagram -- eMMC Device Controller
  • eMMC 5.1 Device Controller
    • Compliant with eMMC 5.1 specification
    • Peak bandwidth of 3.2 Gbps or 400 MB/s
    • Additional Data Strobe signal for HS400 mode
  • SD/eMMC in GF (12nm)
    • Compliant with eMMC5.1 and SD 6.0
    • Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
    • Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
    • Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
  • Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
    • Compliant with SD HCI specification
    • CQE capable of reordering task execution based on priority
    • Data prefetching for back to back tasks—further improves random IOPS
    • Low-power features with power gating and multi-power rails
  • SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
    • Compliant with eMMC5.1 and SD 6.0
    • Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
    • Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
    • Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
  • eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
    • • Suitable for Transmitter, Receiver, and Data Strobe pins
    • VCORE Pre driver voltage
    • VCCQ Post driver voltage
    • TJ Junction temperature
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